The present invention relates to monolithic circuit topologies which function to magnify the apparent size of a capacitor that is used in a AC filtering or compensation applications.
In integrated circuit designs, there is occasionally the need to use a relatively large capacitance to achieve the desired circuit performance. For example, to stabilize the feedback loop found in a phase lock loop or in a linear switch-mode voltage regulator, a low frequency zero can be installed in the loop gain to enhance the phase margin and improve transient response. Larger capacitance values on the order of tens of picofarads or more may be required, depending on the particular loop crossover frequency and circuit impedance levels.
Unfortunately, a substantial die area may be incurred in the construction of these capacitors. In particular, in some 0.6 uM CMOS processes, a poly-poly capacitor may require about 800 μM2 per picofarad of capacitance. Alternatively, larger capacitors may also be placed external to the die, but at the expense of a pin-out increase and reduced convenience at the application level.
A capacitance multiplier circuit in which a smaller monolithic capacitance appears to have the current and □V/□T characteristic of a larger capacitor may be useful in these instances. The reduction in chip area can reduce the IC cost and/or leave extra area for other circuits on the die.
Capacitance multiplier circuits are known in the prior art. U.S. Pat. Nos. 5,900,771 and 6,084,475 describe both bipolar and CMOS capacitance multipliers using basic current mirror techniques. In accordance with both of these references, the circuit topology is arranged to sum a capacitive current directly into a diode-connected device (gate and drain tied on MOS or CB in bipolar), which serves as the input side of a mirror structure.
In terms of frequency response, the known mirror-based approaches have a bandwidth limit imposed by the series resistance of the sensing path. At high frequencies, this limit causes the circuit to appear to be resistive rather than to exhibit the desired capacitive behavior. In terms of the AC pole-zero response, a zero is inadvertently inserted by the series resistance. Hence, the range and performance of filter and compensator networks using these multipliers may very well be limited.
By contrast, the present invention employs a cascoded current summing topology, in which a capacitive current is summed into a virtual node formed by the source-drain connection of two transistors. This arrangement reduces the series resistance of the current sensing path. As a consequence, the present multiplier circuit remains capacitive at higher frequencies than are possible using prior art mirror approaches. This attribute is beneficial to the performance of filters and compensator networks in which the capacitance multiplier may be used. In particular, the resulting higher bandwidth permits greater design flexibility since the zero frequency has been pushed higher, often outside of the critical range.
In accordance with the illustrated preferred embodiment of the present invention, a capacitance multiplier circuit is provided having two external nodes (an output node and a return node). Between these two external nodes, the circuit electrically multiplies the apparent size of a capacitor having its first terminal connected to the output node and its second terminal connected to a first internal node of the circuit.
The first internal node is connected to the second terminal of the capacitor and to a first MOS transistor drain terminal and a second MOS transistor source terminal. At a second internal node, the gate of the first MOS transistor is connected to the drain terminal of the second MOS transistor. In addition, the gate terminal of a third MOS transistor is connected to the second internal node together with the first terminal of an external bias current source. The drain and source terminals of the third MOS transistor are connected between the output node and the return node, respectively.
The amount of capacitance multiplication by the circuit of the present invention is determined by a ratio factor K, greater than unity, that is representative of the physical sizes of the first and third transistors. That is, the third transistor is K times larger than the first transistor.